1. Field of the Invention
The present invention is directed to memory device, and in particular, to a flash memory device in which a memory cell array is divided into a plurality of sector units.
2. Background of the Related Art
An Electrically Programmable Read-Only Memory (EPROM) is a flash memory device that users can program byte by byte with data. When an erasing operation is performed, the data stored in each cell of a memory cell array are erased, and the EPROM can subsequently be re-programmed again.
The data stored in all the cells of the memory cell array can be erased at one time by an erasing operation. To prevent the data stored in all the cells from being erased at one time, a conventional memory cell array is divided into a plurality of sectors, and the erasing operation is performed by sectors. For instance, U.S. Pat. No. 5,245,570 titled "Floating gate non-volatile memory blocks and select transistors" discloses such conventional art.
FIG. 1 is a schematic diagram illustrating a conventional flash memory device. As illustrated in FIG. 1, the flash memory device includes a memory cell array 10, a plurality of word line decoders 21.about.26, a bit line decoder 30, and a plurality of sector select decoders 41, 42 that divide the memory cell array 10 into a plurality of memory sectors 11, 12. Respective memory cells of the memory cell array 10 are commonly connected to the word line decoders 21.about.26 through word lines W/L1, W/L2, . . . , W/Ln and to the bit line decoder 30 through global bit lines B/L1, B/L2, . . . , B/Ln.
The memory sectors 11, 12 respectively include sector select units 110, 120. In accordance with an operation of the sector select decoders 41, 42, the sector select units 110, 120 control the connection between each cell of the memory sectors 11, 12 and the bit line decoder 30.
FIG. 2 is a detailed diagram illustrating the memory cell array of in FIG. 1. The gates of the cells E11.about.En4 of the memory sector 11 are respectively connected to the word lines W/L1.about.W/Ln and the drains of the cells E11.about.En4 are connected to local bit lines B/LL1.about.B/LL4. The local bit lines B/LL1.about.B/LL4 commonly connect the drains of memory cells of the memory cell array 10 located in corresponding columns. In addition, the sources of the respective cells inside the memory sector 11 are commonly connected. The sector select unit 110 includes a plurality of select transistors L1.about.T4 for selectively connecting the local bit lines B/LL1.about.B/LL4 with the global bit lines B/L1, B/L2. The gates of the select transistors L1.about.T4 are connected to the sector select decoder 41 through sector select lines SL1, SL2. As shown in FIG. 2, the plurality of select transistors L1.about.T4 are NMOS transistors.
The operation of the conventional flash memory device of FIGS. 1 and 2 will now be described. When the sector select decoder 41 outputs a predetermined voltage through one of the sector select lines SL1, SL2 under the condition that one of the word lines W/L1.about.W/Ln and one of the global bit lines B/L1, B/L2 are enabled, one of the memory cells E11.about.En4 in the memory sector 11 is selected. For example, when the sector select decoder 41 outputs a high-level voltage through the sector select line SL1 and outputs a low-level voltage through the sector select line SL2, the select transistors T2, T4 with their gates connected to the sector select line SLI are turned on. Further, the select transistors L1, T3 with their gates connected to the sector select line SL2 are turned off. As the select transistors T2, T4 are turned on, the global bit lines B/L1, B/L2 are respectively connected to the local bit lines B/LL2, B/LL4. If the first word line W/L1 and the first global bit line B/L1 are enabled, memory cell E12 is selected.
The reading, writing and erasing operations will now be described with reference to FIG. 3. The reading and writing operations are performed using the respective word lines, but the erasing operation is simultaneously performed on all the memory cells inside the entire sector.
FIG. 3 indicates the voltage levels applied to the respective terminals of the memory cell while the reading, writing and erasing operations are performed. As shown in FIG. 3, the reading operation is performed on a selected memory cell when a word line voltage, which is a gate voltage of the selected memory cell, is a power supply voltage VCC, a bit line voltage, which is a drain voltage, is in the range between 1 V and 1.5 V and a ground voltage, which is a source voltage, is 0 V.
As shown in FIG. 3, the writing operation is performed on the selected memory cell when a voltage of 8 V to 10 V is applied to the gate, a voltage of 5 V to 7 V is applied to the drain and a voltage of 0 V is applied to the source of the selected memory cell. During the writing operation, electric charges may move from a substrate to a floating gate, and thereby a disturbance phenomenon may occur to the memory cells in the proximity of the memory cells connected to the same word line. To prevent such disturbance phenomenon, the gate voltage should be limited to a proper value.
As further shown in FIG. 3, the erasing operation is performed when a voltage of -8 V to -12 V is applied to the gate of the selected memory cell, a voltage of 5 V to 7 V is applied to the source, and the drain is in a floating condition. That is, when the corresponding select transistor is turned off, the drain of the memory cell being connected to the select transistor is put in a floating condition. In the case that the voltage of the word line is set to be between -8 V to -12 V, the data of the selected memory cell is erased. Meanwhile, as the respective gate voltages of the cells in sectors (e.g., sector 12 not illustrated) not selected are set to be 0 V, the erasing operation is not performed thereon.
The erasing operation is simultaneously performed on all the memory cells E11.about.En4 inside the entire memory sector 11. That is, when a voltage of -8 V to -12 V is applied through the word lines W/L1.about.W/Ln and the select transistors T1.about.T4 are turned off, the erasing operation is performed on all the memory cells E11.about.En4 at the same time.
As described above, the conventional flash EPROM has various disadvantages. In the conventional flash EPROM art, to enable the memory cells during the erasing and writing operations, a word line decoder is required for each word line. Accordingly, if there are 256 word lines, 256 word line decoders must be correspondingly provided. Layout is important in a semiconductor integrated circuit. Size of the memory cells can be decreased to reduce the entire layout. However, even if the size of the memory cells is decreased, unless the design of the peripheral circuits is reduced, it is difficult or impossible to position the word line decoders fitting to the size of the cells. Therefore, even with decreased cell size, if the word line decoder size is not reduced, the size of the word line decoder is relatively increased. Accordingly, to decrease the size of the layout efficiently, it is necessary to reduce a proportion of the word line decoder layout in the entire layout.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.